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copyright ? cirrus logic, inc. 2010 (all righ ts reserved) preliminary product information this document contains information for a new product. cirrus logic reserves the right to mo dify this product without notice. http://www.cirrus.com dual high-performance amplifier & ? modulator features ? high input impedance differential amplifier ? ultra-low input bias: < 1 pa ? max signal amplitude: 5 vpp differential ? fourth order delta-sigma ( ? ) modulator ? signal bandwidth: dc to 2 khz ? common mode rejection: 110 db cmrr ? differential analog input, digital ? output ? multiplexed inputs: ina, inb, 800 termination ? selectable gain: 1x, 2x, 4x, 8x, 16x, 32x, 64x ? excellent amplifier noise performance ?1.5 vpp between 0.1 hz and 10 hz ? 11 nv / hz from 200 hz to 2 khz ? high modulator dynamic range ? 126 db snr @ 215 hz bw (2 ms sampling) ? 123 db snr @ 430 hz bw (1 ms sampling) ? low total harmonic distortion ? ?118 db thd typical (0.000126%) ? ?108 db thd maximum (0.0004%) ? low power consumption ? normal operation: 6.5 ma per channel ? power down: 15 a per channel max ? dual power supply configuration ? va+ = +2.5 v; va? = ?2.5 v; vd = +3.3 v description the cs5374 combines two marine seismic analog mea- surement channels into one 7 mm x 7 mm qfn package. each measurement c hannel consists of a high input impedance programmable gain differential amplifi- er that buffers analog signals into a high-performance, fourth-order ? modulator. the low-noise ? modulator converts the analog signal into a one-bit serial bit stream suitable for the cs53 76a digital filter. each amplifier has two sets of external inputs, ina and inb, to simplify system design as inputs from a hydro- phone sensor or the cs4373a test dac. an internal 800 termination can also be selected for noise tests. gain settings are binary weighted (1x, 2x, 4x, 8x, 16x, 32x, 64x) and match the cs 4373a test dac output at- tenuation settings for full-scal e testing at all gain ranges. both the input multiplexer and gain are set by registers accessed through a standard spi? port. each fourth-order ? modulator has very high dynamic range combined with low total harmonic distortion and low power consumption. it c onverts differential analog signals from the amplifier to an oversampled ? serial bit stream which is decimated by the cs5376a digital filter to a 24-bit output at the final output word rate. ordering information see page 43 . ina1+ inb1+ mux1 mux2 inb1- ina1- guard1 + - - + 400 400 ina2+ inb2+ inb2- ina2- + - - + 400 400 reset, clock, and synchronization inr1- va+ mflag1 mclk msync mflag2 mdata2 gain1 gain2 guard2 inr2- inr2+ 4 th order modulator 4 th order modulator inf1- inf1+inr1+ rst spi tm serial interface sdi sdo sclk cs inf2+ inf2- out2- out2+ out1+ out1- cs5374 va- gnd vd vref- vref+ va+ va- mdata1 sep '10 ds862f2 cs5374
cs5374 cs5374 2 table of contents 1. characteristics and specificatio ns ............... ................................ ............. ........... 4 specified operating conditions .............. ................ ....................................... ........... 4 absolute maximum ratings ........ ................................ ....................................... ........... 4 thermal characteristics ............................................................................................. 5 analog characteristics ............................................................................................... 5 performance specifications .... ................................ ....................................... ........... 7 channel performance plots ....................... ............................................................... 9 digital characteristics .............................................................................................. 10 spi? interface timing (external master) ............................................................ 12 power supply characteristics ............................................................................... 13 2. general description..................................................................................................... 14 3. amplifier operation ................................... ................................................................... 16 3.1 amplifier inputs ? ina, inb .......................................................................................... 16 3.1.1 multiplexer settings ? mux ............................................................................... 16 3.1.2 gain settings ? gain ........................................................................................ 16 3.2 amplifier outputs ? outr, outf ............................................................................... 16 3.2.1 guard output ? guard.................................................................................... 16 3.3 differential signals ........................................................................................................ 17 4. modulator operation .................................................................................................. 18 4.1 modulator anti-alias filter ............................................................................................. 18 4.2 modulator inputs ? inr, inf ........................................................................................ 19 4.2.1 modulator input impedance ................ ................................................................ 19 4.2.2 modulator idle tones ? ofst ........................................................................... 19 4.3 modulator output ? mdata ........................................................................................ 19 4.3.1 modulator one?s density ..................................................................................... 19 4.3.2 decimated 24-bit output ..................................................................................... 19 4.4 modulator stability ? mflag....................................................................................... 20 4.5 modulator clock input ? mclk.................................................................................... 20 4.6 modulator synchronization ? msync ......... ................................................................ 20 5. spi tm serial port ............................................................................................................. 21 5.1 spi pin descriptions ..................................................................................................... 21 5.2 spi serial transactions................................................................................................. 21 5.3 spi registers ............................................................................................................... .23 5.3.1 version ? 0x00............................................................................................... 23 5.3.2 amp1cfg ? 0x01 ............................................................................................. 23 5.3.3 amp2cfg ? 0x02 ............................................................................................. 23 5.3.4 adccfg ? 0x03................................................................................................ 24 5.3.5 pwrcfg ? 0x04 ............................................................................................... 24 5.4 example: cs5374 configurati on by an external spi master ........................................ 24 5.5 example: cs5374 configuration by the cs5376a spi 2 port ...................................... 25 5.5.1 cs5376a spi 1 transactions ............................................................................. 25 6. power modes .................................................................................................................. .. 29 6.1 normal operation .......................................................................................................... 29 6.2 power down, mclk enabled..................... ................................................................... 29 6.3 power down, mclk disabled ....................................................................................... 29 7. voltage reference ....................................................................................................... 30 7.1 vref power supply ..................................................................................................... 30 7.2 vref rc filter ............................................................................................................. 3 0 7.3 vref pcb routing ....................................................................................................... 30 7.4 vref input impedance................................................................................................. 30 7.5 vref accuracy............................................................................................................. 31 8. power supplies .............................................................................................................. 32 8.1 analog power supplies ................................................................................................. 32 8.2 digital power supply ..................................................................................................... 32 8.3 power supply bypassing .............................................................................................. 32
cs5374 cs5374 3 8.4 pcb layers and routing............................................................................................... 33 8.5 power supply rejection ................................................................................................ 33 8.6 scr latch-up considerations....................................................................................... 33 8.7 dc-dc converters ........................................................................................................ 33 9. spi tm register summary................................................................................................ 34 9.1 version: 0x00 ............................................................................................................ 35 9.2 amp1cfg: 0x01 ........................................................................................................... 36 9.3 amp2cfg: 0x02 ........................................................................................................... 37 9.4 adccfg: 0x03 ............................................................................................................. 38 9.5 pwrcfg: 0x04 ............................................................................................................ 38 10. pin descriptions ........................................................................................................... .. 40 11. package dimensions ...................................................................................................... 42 12. ordering information ................................................................................................. 43 13. environmental, manufacturing, & han dling information ........................... 43 14. revision history ........................................................................................................... .44 list of figures figure 1. external anti-alias filt er components.............................................................................. 6 figure 2. cs5374 am plifier noise performance ..................... ........................................................ 7 figure 3. cs5374 noise performance (1x gain) ........................................................................... 9 figure 4. cs5374 + cs4373a te st dac dynamic performance ................................................... 9 figure 5. digital rise and fall times sync from external system. .............................................. 10 figure 6. system synchronization diagram.................................................................................. 10 figure 7. mclk / msync timing detail ....................................................................................... 11 figure 8. sdi write timing in spi slave mode ............................................................................. 12 figure 9. sdo read timing in spi slave mode ........................................................................... 12 figure 10. cs5374 system block diagram................................................................................... 14 figure 11. cs5374 connection diagram ...................................................................................... 15 figure 12. cs5374 to cs5376a digital interface.......................................................................... 15 figure 13. cs5374 amplifier block diagram........... ...................................................................... 16 figure 14. cs5374 modulator block diagram............ ................................................................... 18 figure 15. spi interface block diagram........................................................................................ 2 1 figure 16. cs5374 (slave) serial transactions with cs5376a (master)...................................... 22 figure 17. power mode diagram .. ................................................................................................ 29 figure 18. voltage refer ence circuit ........................................................................................... .30 figure 19. power supply diagram ................................................................................................ 32 figure 20. hardware version id register version .................................................................... 35 figure 21. amplif ier 1 configuration register amp1cfg............................................................. 36 figure 22. amplif ier 2 configuration register amp2cfg............................................................. 37 figure 23. modulator 1 & 2 configuration register adccfg....................................................... 38 figure 24. power configur ation register pwrcfg ..................................................................... 39 list of tables table 1. 24-bit output coding ................................................................................................. ..... 20 table 2. spi configuration registers .............. ............................................................................ .23 table 3. digital selections for gain and input mux control ......................................................... 23 table 4. example spi transactions to write and read the cs5374 configuration registers .... 24 table 5. example cs5376a spi 1 transactions to write and read the gpcfg0 register ....... 25 table 6. example cs5376a spi 1 transactions to write the cs5374 amp1cfg register ....... 26 table 7. example cs5376a spi 1 transactions to write amp2cfg and adccfg .................. 27 table 8. example cs5376a spi 1 transactions to write the cs5374 pwrcfg register ......... 28
cs5374 cs5374 4 1. characteristics and specifications ? min/max characteristics and s pecifications are guaranteed over the specified operating conditions. ? typical performance characteristics and specificat ions are derived from measurements taken at nom- inal supply voltages and t a = 25 , specified operating conditions notes: 1. va- must always be the most-negative input vo ltage to avoid potential scr latch-up conditions. 2. by design, a 2.500 v voltage reference input results in the best si gnal-to-noise performance. 3. channel-to-channel gain accuracy is directly propor tional to the voltage reference absolute accuracy. 4. vref inputs must satisfy: va- absolute maximum ratings warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not gu aranteed at these extremes. notes: 5. transient currents up to 100 ma will not cause scr latch-up. 6. includes continuous over-voltage conditions on the analog input pins. parameter symbol min nom max unit bipolar power supplies voltage reference thermal parameter symbol min max unit dc power supplies positive analog negative analog digital va+ va- vd -0.3 -6.8 -0.3 6.8 0.3 6.8 v v v analog supply differential [(va+) - (va-)] va diff -6 . 8v digital supply differential [(vd) - (va-)] vd diff -6 . 8v input current, any pin except supplies ( note 5, 6 )i in -+ 10 ma input current, power supplies ( note 5 )i pwr -+ 50 ma output current ( note 5 )i out -+ 25 ma power dissipation pd - 500 mw analog input voltages v ina (va-)-0.5 (va+)+0.5 v digital input voltages v ind -0.5 (vd)+0.5 v storage temperature range t stg -65 150 c
cs5374 cs5374 5 thermal characteristics analog characteristics notes: 7. common mode signals pass through the differenti al amplifier architecture and are rejected by the modulator cmrr. 8. output impedance characteristic s are approximate and can vary up to 30% depending on process parameters. parameter symbol min typ max unit ambient operating temperature t a -10 - 70 c storage temperature range t str -65 - 150 c allowable junction temperature t jct --125c junction to ambient thermal impedance (4-layer pcb) ja -26-c/w parameter symbol min typ max unit amplifier inputs signal frequencies bw dc - 2000 hz differential gain gain x1 - x64 common mode gain ( note 7) gain cm -x1- common mode voltage v cm - (va-)+2.5 -v voltage range (signal + vcm) x1 x2 - x64 v in (va-)+0.7 (va-)+0.7 - - (va+)-1.25 (va+)-1.75 v full scale differential input x1 x2 x4 x8 x16 x32 x64 v infs - - - - - - - - - - - - - - 5 2.5 1.25 625 312.5 156.25 78.125 v pp v pp v pp mv pp mv pp mv pp mv pp differential input impedance z indiff -1, 20- t , pf common mode input impedance z incm - 0.5, 40 - t , pf input bias current i in -140pa amplifier outputs full scale output, differential v out --5v pp output voltage range (signal + vcm) v rng (va-)+0.5 - (va+)-0.5 v output impedance ( note 8 )z out -40- output impedance drift ( note 8 )z tc -0.38- / c output current i out --+ 25 ma load capacitance c l --100nf guard outputs guard output voltage v guard -v cm -v guard output impedance ( note 8 )zg out -500- guard output current ig out --40 a guard load capacitance cg l --100pf
cs5374 cs5374 6 analog characteristics (cont.) notes: 9. the upper bandwidth limit is determined by the selected digital filter cut-off frequency. 10. anti-alias capacitors are discrete external componen ts and must be of good quality (c0g, npo, poly). poor-quality capacitors will d egrade total harmonic distortion (thd) performance. see figure 1 for external anti-alias filter connections. 11. maximum integrated noise over the measurement ban dwidth for the voltage reference device attached to the vref inputs. parameter symbol min typ max unit modulator inputs input signal frequencies ( note 9) v bw dc - 2000 hz full-scale differential ac input v ac --5v pp full-scale differential dc input v dc -2.5 - 2.5 v dc input common mode voltage v cm - (va-)+2.5 -v input voltage range (v cm signal) v rng (va-)+0.7 - (va+)-1.25 v differential input impedance inr inf zdif inr zdif inf - - 20 1 - - k m single-ended input impedance inr inf zse inr zse inf - - 40 2 - - k m external anti-alias filter series resistance ( note 10 ) differential capacitance r aa c diff - - 680 20 - - nf vref inputs [vref+] - [vref-] ( note 2, 3 ) vref - 2.500 - v vref- ( note 4 )vref- - va- - v vref input current vref ii -120- a vref input noise ( note 11 )vref in --1v rms modulator inr+ inf+ inf- inr- 20nf c0g 20nf c0g 680 amplifier out+ out- 680 680 680 cs5374 figure 1. external anti-alias filter components
cs5374 cs5374 7 performance specifications notes: 12. dynamic range defined as 20 log [(rms full scale) / (rms idle noise)] where idle noise is measured with the amplifier input terminated. dynamic range is dominated by high-frequency quantization noise at the 1/4 ms rate and amplifier noise at high gain. 13. tested with a 31.25 hz sine wave at 1 ms sampling rate and -1 db amplitude. parameter symbol min typ max unit amplifier noise voltage noise f 0 = 0.1 hz to 10 hz vn pp -1.5 3 v pp voltage noise density f 0 = 200 hz to 2 khz vn d -11 14 current noise density in d -20 - channel dynamic range dynamic range (1/4 ms) dc to 1720 hz (1x gain, multiple owrs) (1/2 ms) dc to 860 hz ( note 9, 12 ) (1ms)dcto 430hz (2 ms) dc to 215 hz (4 ms) dc to 108 hz (8 ms) dc to 54 hz (16 ms) dc to 27 hz snr - - 121 - - - - 105 120 123 126 129 131 135 - - - - - - - db db db db db db db dynamic range 1x (multiple gains, 1 ms owr) 2x ( note 9, 12 )3x 8x 16x 32x 64x snr 121 - - - - - - 123 122 120 116 111 105 98 - - - - - - - db db db db db db db channel distortion total harmonic distortion 1x ( note 13 )2 x 4x 8x 16x 32x 64x thd - - - - - - - -118 -119 -119 -119 -118 -115 -112 -108 - - - - - - db db db db db db db nv/ hz fa/ hz 0 5 10 15 20 0 200 400 600 800 1000 1200 1400 1600 1800 2000 frequency (hz) cs5374 amplifier in-band noise noise density (nv/rthz) 0 100 200 300 400 0.1 1 10 100 1k frequency (hz) cs5374 amplifier wide band noise noise density (nv/rthz) 10k 100k 1m figure 2. cs5374 amplifier noise performance
cs5374 cs5374 8 performance specif ications (cont.) notes: 14. channel gain is the nominal full-scale 24-bit output code from the cs5376a digital filter for a 5 v pp differential signal into the cs5374 analog in puts at 1x gain. value is offset corrected. 15. absolute gain accuracy tests the matching of 1x gain across multiple cs5374 channels in a system. 16. relative gain accuracy tests the tra cking of 2x, 4x, 8x, 16x, 32x, 64x gai n relative to 1x gain on a single cs5374 channel. 17. specification is for the parameter over the spec ified temperature range and is for the cs5374 device only. it does not include the e ffects of external components. 18. offset voltage is tested with the amplif ier inputs connected to the internal 800 termination. 19. the offset after calibration specification is measured from the digitally calibrated output codes of the cs5376a digital filter. 20. offset calibration is performed in the cs5376a digital filter and includes the full-scale signal range. parameter symbol cs5374 unit min typ max channel gain accuracy channel gain, offset corrected ( note 3, 14 )gain lsb -6101194 0xa2e736 - - 6101194 0x5d18ca lsb lsb absolute gain accuracy ( note 3, 15 )gain abs -1+ 2% relative gain accuracy 2x ( note 16 )4 x 8x 16x 32x 64x gain rel -0.3 - - - - - -0.1 -0.1 0.1 0.4 0.4 0.3 0.1 - - - - - % % % % % % gain drift ( note 17) gain tc -25-ppm/c channel offset accuracy amplifier offset vo ltage, input referred ( note 18 )ofst amp - 250 750 v amplifier offset drift, input referred ( note 17 )ofst atc -0.3-v/c modulator offset voltage, differential (ofst =1) ofst mod -1- mv modulator offset voltage, channel 1 (ofst =0) ofst mod1 --60- mv modulator offset voltage, channel 2 (ofst =0) ofst mod2 --35- mv modulator offset drift ( note 17 )ofst mtc -1-v/c offset after calibration ( note 19 )ofst cal -1- v offset calibration range ( note 20 )ofst rng -100- %fs channel cmrr and crosstalk common mode rejection ratio cmrr - 110 - db crosstalk, amplifier multiplexed inputs cxt mi --130- db crosstalk, channel-to-channel cxt cc --130- db
cs5374 cs5374 9 channel performance plots figure 3. cs5374 noise performance (1x gain) figure 4. cs5374 + cs4373a test dac dynamic performance
cs5374 cs5374 10 digital characteristics notes: 21. device is intended to be driven with cmos logic levels. 22. guaranteed by design and/or characterization. parameter symbol min typ max unit digital inputs high-level input voltage ( note 21 )v ih 0.6*vd - vd v low-level input voltage ( note 21 )v il 0.0 - 0.8 v input leakage current i in -110 a digital input capacitance c in -9- pf input rise times except mclk t rise --100ns input fall times except mclk t fall --100ns digital outputs high-level output voltage, i out =-40 av oh vd - 0.3 - - v low-level output voltage, i out =40 av ol --0.3v high-z leakage current i oz -110 a digital output capacitance c out -9- pf output rise times (note 22) t rise --100ns output fall times (note 22) t fall --100ns 0.9 * vd 0.1 * vd t fa ll t rise figure 5. digital rise and fall times sync from external system. mclk msync t mdata tdata 0 sync mflag figure 6. system synchronization diagram sync from external. mclk, msync, tdata from cs5376a. mdata, mflag from cs5374.
cs5374 cs5374 11 digital characteristics (cont.) notes: 23. mclk is generated by the cs5376a digital filter. if mclk is disabled, the cs5374 device automatically enters a power-down state. see power supply characteristics for typical power-down timing. 24. msync is generated by the cs5376a digital filter and is latched by cs5374 on mclk falling edge, synchronization instant ( t 0 ) is on the next mclk rising edge. 25. decimated, filtered, and offset-corrected 24-bit output word from the cs5376a digital filter. parameter symbol min typ max unit master clock input mclk frequency ( note 23 )f mclk - 2.048 - mhz mclk duty cycle mclk dtc 40 - 60 % mclk rise time t rise - - 50 ns mclk fall time t fall - - 50 ns mclk jitter (in-band or aliased in-band) mclk ibj --300ps mclk jitter (out-of-band) mclk obj --1 ns master sync input msync setup time to mclk falling ( note 24 )t mss 20 366 - ns msync period ( note 24 )t msync 40 976 - ns msync hold time after mclk falling ( note 24 )t msh 20 610 - ns mdata output mdata output bit rate f mdata -512- kbits/s mdata output one?s density range ( note 22 )mdat 1d 14 - 86 % full-scale output code, offset corrected ( note 25 )mdat fs 0xa2e736 - 0x5d18ca mclk msync t 0 t mss 1 / f mclk t msync t msh mdata mflag 1 / f mdata figure 7. mclk / msync timing detail
cs5374 cs5374 12 spi? interface timing (external master) parameter symbol min typ max unit sdi write timing cs enable to valid latch clock t 1 60 - - ns data set-up time prior to sck rising t 2 60 - - ns data hold time after sck rising t 3 60 - - ns sck high time t 4 120 - - ns sck low time t 5 120 - - ns sck falling prior to cs disable t 6 60 - - ns sdo read timing sck falling to new data bit t 7 - - 90 ns sck high time t 8 120 - - ns sck low time t 9 120 - - ns sck falling hold time prior to cs disable t 10 60 - - ns msb msb - 1 lsb t 6 t 5 t 4 t 3 t 2 t 1 cs sdi sck figure 8. sdi write timing in spi slave mode msb msb - 1 lsb t 9 t 8 t 7 cs sdo sck t 10 figure 9. sdo read timing in spi slave mode
cs5374 cs5374 13 power supply characteristics notes: 26. all outputs unloaded. digital inputs forced to vd or gnd respectively. amplif ier inputs connected to the 800 internal termination. parameter symbol min typ max unit power supply current, ch1 + ch2 combined analog power supply current ( note 26 )i a -1316 ma digital power supply current ( note 26 )i d -50100 a power supply current, ch1 or ch2 only analog power supply current ( note 26 )i a -6.58 ma digital power supply current ( note 26 )i d -2550 a power down current, mclk enabled analog power supply current ( note 26 )i a - 150 250 a digital power supply current ( note 26 )i d -1075 a power down current, mclk disabled analog power supply current ( note 26 )i a -215 a digital power supply current ( note 26 )i d -115 a power down timing (after mclk disabled) ( note 22 )pd tc -40- s power supply rejection power supply rejection ratio ( note 22 )psrr - 100 - db
cs5374 cs5374 14 2. general description the cs5374 combines two marine seismic analog measurement channels in to one 7 mm x 7 mm qfn package. each measurement channel consists of a high input impedance progr ammable gain differen- tial amplifier that buffers analog signals into a high-performance, fourth-order ? modulator. the low-noise ? modulator convert s the analog signal into a one-bit serial bit stream suitable for the cs5376a digital filter. each amplifier has two sets of external inputs, ina and inb, to simplify sy stem design as inputs from a hydrophone sensor or the cs4373a test dac. an internal 800 termination can also be selected for noise tests. gain settings are binary weighted (1x, 2x, 4x, 8x, 16x, 32x, 64x) and match the cs4373a test dac output attenuation settings for full-scale testing at all gain ranges . both the input multiplex- er and gain are set by re gisters accessed through a standard spi? port. each fourth-order ? modulator has very high dy- namic range combined with low total harmonic dis- tortion and low power c onsumption. it converts differential analog signals from the amplifier to an oversampled ? serial bit stream which is decimat- ed by the cs5376a digital fi lter to a 24-bit output at the final output word rate. figure 10 shows the system-lev el architecture of a 4-channel acquisition system using two cs5374, one cs5376a digital filter and one cs4373a test dac. figure 11 and figure 12 shows connection dia- grams for the cs5374 device when connected to the cs5376a digital filter . hydrophone sensor hydrophone sensor hydrophone sensor hydrophone sensor ds modulator digital filter cs5376a test dac microcontroller or configuration eeprom system telemetry amp cs4373a cs5374 ds modulator amp m u x ds modulator amp m u x cs5374 ds modulator amp m u x m u x figure 10. cs5374 system block diagram
cs5374 cs5374 15 figure 11. cs5374 connection diagram a ina1+ ina1- mux1 mux2 inb1- inb1+ guard1 + - - + 400 400 inb2+ inb2- ina2- ina2+ + - - + 400 400 reset, clock, and synchronization inr1- va+ mflag1 mdata1 mclk msync mflag2 mdata2 gain1 gain2 guard2 inr2- inr2+ 4 th order ? modulator 4 th order ? modulator inf1- inf1+ inr1+ rst spi tm serial communications interface sdi sdo sclk cs inf2+ inf2- out2- out2+ out1+ out1- cs5374 va- gnd vd+ vref- vref+ va+ va- hydrophone sensor hydrophone sensor va- 0.1 va+ 0.1 f f test dac cs4373a 0.02 c0g 0.02 c0 g 680 680 680 680 f f 0.02 c0g 0.02 c0g 680 680 680 680 f f va- 0.1 va+ 0.1 f f 0.01 f 2.5v precision voltage reference to cs5376a digital control figure 12. cs5374 to cs5376a digital interface reset, clock, and synchronization mflag1 mdata1 mclk msync mflag2 mdata2 4 th order ? modulator 4 th order ? modulator rst spi tm serial communications interface sdi sdo sclk cs cs5374 msync mclk clock and synchronization modulator data interface spi 2 serial peripheral interface 2 reset mflag1 mdata1 mflag2 mdata2 si1 so sck2 cs0 cs5376a external reset controller
cs5374 cs5374 16 3. amplifier operation the cs5374 high-impeda nce, low-noise cmos differential input, differen tial output amplifiers are optimized for precision an alog signals between dc and 2 khz. they have mu ltiplexed inputs and pro- grammable gains of 1x, 2x, 4x, 8x, 16x, 32x, and 64x. the performance of th is amplifier makes it ideal for low-frequenc y, high-dynamic-range ap- plications requiring low distortion and minimal power consumption. 3.1 amplifier inputs ? ina, inb the amplifier analog inpu ts are designed for high- impedance differential hydrophone sensors and so have very low input bias below 1 pa. 3.1.1 multiplexer settings ? mux input multiplexing simpli fies system connections by providing separate input s for a sensor and test dac (ina, inb) as well as an internal termination for noise tests. the multiplexer determines which input is connected to th e amplifier, and is set through internal configuration registers accessed through the spi port, see the ?spi tm register sum- mary? on page 34 for more information. although a mux selection is provided to enable the ina and inb switches simultaneously, significant current should not be driven through them in this mode. the cs5374 mux switches will maintain good linearity only with minimal signal current. 3.1.2 gain settings ? gain the cs5374 supports gain ranges of 1x, 2x, 4,x 8x, 16x, 32x, and 64x. ampl ifier gain is selected using internal configuration re gisters accessed through the spi port, see the ?spi tm register summary? on page 34 for more information. 3.2 amplifier outputs ? outr, outf the amplifier analog outputs are externally sepa- rated into rough / fine ch arge signals to connect into the modulator inputs. each differential output requires two series resist ors and a diffe rential ca- pacitor to create the modulat or anti-alias rc filter. 3.2.1 guard output guard the guard pin outputs the common mode volt- age of the selected anal og signal input. it can be used to drive the cable shield between a high-im- pedance sensor and the amplifier inputs. driving the cable shield with the analog signal common mode voltage minimizes le akage and improves sig- nal integrity from high-impedance sensors. the guard output is defined as the midpoint voltage between the + and ? halves of the currently ina1+ inb1+ mux1 inb1- ina1- guard1 + - - + 400 400 gain1 out1+ out1- figure 13. cs5374 am plifier block diagram
cs5374 cs5374 17 selected differential input signal, and will vary as the signal common mode varies. the guard out- put will not drive a signif icant load, as it can only provide a shielding voltage. 3.3 differential signals analog signals into and out of the amplifiers are differential, consisting of two halves with equal but opposite magnitude varyi ng about a common mode voltage. a full-scale 5 v pp differential signal centered on a ?0.15 v common mode can have: sig+ = ?0.15 v + 1.25 v = 1.1 v sig? = ?0.15 v ? 1.25 v = ?1.4 v sig+ is +2.5 v relative to sig- for the reverse case: sig+ = ?0.15 v ? 1.25 v = ?1.4 v sig? = ?0.15 v + 1.25 v = 1.1 v sig+ is ?2.5 v relative to sig- the total swing for sig+ relative to sig? is (+2.5 v) ? (?2.5 v) = 5 v pp . a similar calculation can be done for sig? relati ve to sig+. note that a 5v pp differential signa l centered on a ?0.15 v common mode voltage never exceeds 1.1 v and never drops below ?1.4 v on ei ther half of the sig- nal. by definition, differential voltages are to be mea- sured with respect to the opposite half, not relative to ground. a multi-meter di fferentially measuring between sig+ and sig? in the above example would properly read 1.767 v rms , or 5 v pp .
cs5374 cs5374 18 4. modulator operation the cs5374 modulators are fourth-order ? type optimized for extremely high-resolution measure- ment of signals betw een dc and 2000 hz. when combined with the internal differential amplifiers, the cs4373a test dac a nd cs5376a digital filter, a small, low-power, self-testing, high-accuracy, multi-channel measurement system results. the modulators have high dynamic range and low total harmonic distortion wi th very low power con- sumption. they are optimized for extremely high- resolution measurement of 5 v p-p or smaller differ- ential signals. they convert analog input signals from the differential amp lifiers to an oversampled serial bit stream which is then passed to the digital filter. the companion cs5376a di gital filter generates the clock and synchroniza tion inputs for the modu- lators while receiving th e one-bit data and over- range flag outputs. the di gital filter decimates the modulator?s oversampled output bit stream to a high-resolution, 24-bit output at the final selected output word rate. 4.1 modulator anti-alias filter the modulator inputs are re quired to be bandwidth limited to ensure modulat or loop stability and pre- vent high-frequency signals from aliasing into the measurement bandwidth. the use of simple, sin- gle-pole, differential, lo w-pass rc filters across the inr and inf input s ensures high-frequency signals are rejected before they can alias into the measurement bandwidth. the approximate ?3 db corn er of the input anti- alias filter is nominally set to the internal analog sampling rate divided by 64, which itself is a divi- sion by 4 of the mclk rate. figure 1 on page 6 illustr ates the cs5374 amplifi- er-to-modulator analog c onnections with input anti-alias filter component s. filter components on the rough and fine pins s hould be identical values for optimum performance, with the capacitor val- ues a minimum of 0.02 f. the rough input can use either x7r or c0g-type capacitors, while the fine input requires c0g-type ca pacitors for optimal lin- earity. using x7r- type capacitors on the fine ana- log inputs will significantl y degrade total harmonic distortion performance. reset, clock, and synchronization inr1- vref- mflag1 mclk msync 4 th order modulator inf1- inf1+inr1+ rst vref+ mdata1 figure 14. cs5374 modulator block diagram ? mclk frequency = 2.048 mhz ? sampling frequency = mclk / 4 = 512 khz ? ?3 db filter corner = sampling freq / 64 = 8 khz ? rc filter = 1 / [ 2
cs5374 cs5374 19 4.2 modulator inputs ? inr, inf the modulator analog inputs are separated into dif- ferential rough and fine signals (inr, inf) to maximize sampling accuracy. the positive half of the differential input si gnal is connected to inr+ and inf+, while the negati ve half is attached to inf? and inr?. the inr pins are switched-ca- pacitor ?rough charge? input s that pre-charge the internal analog sampling capac itor before it is con- nected to the inf fine input pins. 4.2.1 modulator input impedance the modulator inputs have a dynamic switched-ca- pacitor architecture and so have a rough charge in- put impedance that is i nversely proportional to the input master clock freque ncy and the input capaci- tor size, [1 / (f c)]. internal to the modulator, the rough inputs (inr) pre-charge the sampling capacitor used by the fine inputs (inf), ther efore the input current to the fine inputs is typically ve ry low and the effective input impedance is an order of magnitude above the impedance of the rough inputs. 4.2.2 modulator idle tones ofst the modulators are delta- sigma-type and so can produce ?idle tones? in the measurement band- width when the differential input signal is a steady- state dc signal near mid-scale. idle tones result from low-frequency patt erns in the output data stream and appear in the measurement spectrum as small tones about -135 db down from full scale. by default the ofst bit in the adccfg register is low and idle tones are eliminated within the modu- lator by adding ?60 mv (channel 1) and ?35 mv (channel 2) of internal di fferential offset during conversion to push idle t ones out of the measure- ment bandwidth. care s hould be taken to ensure external offset voltages do not negate the internally added differential offset, or idle tones will reap- pear. 4.3 modulator output ? mdata the cs5374 modulators are designed to operate with the cs5376a digital filter. the digital filter generates the modulator clock and synchronization signals (mclk and msync) while receiving back the modulator one-bit ? conversion data and over-range flag (mdata and mflag). 4.3.1 modulator ones density during normal operation the cs5374 modulators output a ? serial bit stream to the mdata pin, with a one?s density propor tional to the differential amplitude of the analog input signal. the output bit rate from the mdata output is a divide-by-four of the input mclk, and so is nominally 512 khz. the mdata output has a 50% one?s density for a mid-scale analog input, approximately 86% one?s density for a positive fu ll-scale analog input, and approximately 14% one?s density for a negative full-scale analog input. on e?s density of the mda- ta output is define d as the ratio of ?1? bits to total bits in the serial bit str eam output; i.e. an 86% one?s density has, on average, a ?1? value in 86 of every 100 output data bits. 4.3.2 decimated 24-bit output when the cs5374 modulators operate with the cs5376a digital filter, the final decimated, 24-bit, full-scale output code range depends if digital off- set correction is enabled. wi th digital offset correc- tion enabled within the digital filter, amplifier ? mclk = 2.048 mhz ? inr internal input capacitor = 20 pf ? impedance = [1 / (2.048 mhz * 20 pf)] = 24 k
cs5374 cs5374 20 offset and the modulator internal offset are re- moved from the fina l conversion result. 4.4 modulator stability ? mflag the cs5374 ? modulators have a fourth-order ar- chitecture which is conditi onally stable and may go into an oscillatory conditi on if the analog inputs are over-ranged more than 5% past either positive or negative full scale. if an unstable condition is detected, the modulator collapses to a first-order sy stem to regain stability and transitions the mfl ag output low-to-high to signal an error condition to the cs5376a digital filter. the mflag output connects to a dedicated input on the digital filter, ca using an error flag to be set in the status byte of the next output data word. the analog input signal must be reduced to within the full-scale range for at least 32 mclk cycles for the modulator to recover from an oscillatory condi- tion. if the analog input re mains over-ranged for an extended period, the modulat or will cycle between fourth-order and first- order operation and the mflag output will be seen to pulse. 4.5 modulator clock input ? mclk the cs5376a digital filter generates the master clock for the cs5374, typi cally 2.048 mhz, from a synchronous clock input from the external system. if mclk is disabled during operation, the cs5374 will enter a power down state after approximately 40 s. by default, mclk is disabled at reset and is enabled by writing the di gital filter config reg- ister. mclk must have low jitt er to guarantee full ana- log performance, requiri ng a crystal- or vcxo- based system clock input to the digital filter. clock jitter on the digital filter clk input directly trans- lates to jitter on mclk. 4.6 modulator synchronization ? msync the cs5374 modulators are designed to operate synchronously with other m odulators in a distribut- ed measurement network, so a rising edge on the msync input resets the in ternal conversion state machine to synchronize analog sample timing. msync is automatically generated by the cs5376a digital filter afte r receiving a synchroni- zation signal from the extern al system, and is chip- to-chip accurate within 1 mclk period. the in- put sync signal to the cs 5376a digital filter sets a common reference time t 0 for measurement events, thereby synchronizing analog sampling across a measurement network. by default, msync generation is disabl ed at reset and is en- abled by writing the digital filter config register. the cs5374 msync input is rising-edge trig- gered and resets the inte rnal mclk counter/divid- er to guarantee synchr onous operation with other system devices. while the msync signal syn- chronizes the internal ope ration of the modulators, by default, it does not sync hronize the phase of the sine wave from the cs 4373a test dac unless en- abled in the digital fi lter tbscfg register. table 1. 24-bit output coding modulator differential analog input signal cs5376a digital filter 24-bit output code offset corrected ch1 ?60 mv offset ch2 ?35 mv offset > + (vref+5%) error flag possible + vref 5d18ca 5adcce 5bcb22 0 v 000000 fdc404 feb258 ? vref a2e736 a0ab3a a1998e > ? (vref+5%) error flag possible for the cs5374 modulator and cs5376a digital filter combination
cs5374 cs5374 21 5. spi tm serial port the cs5374 spi interface is a slave serial port de- signed to interface with the cs5376a spi 2 port. spi commands from th e cs5376a write and read the cs5374 configuration registers to control hard- ware operation. a block diagram of the cs5374 spi serial interface is shown in figure 15, and connections to the cs5376a spi 2 port are shown in figure 12 on page 15. 5.1 spi pin descriptions rst ? pin 37 hardware reset input pin, active low. defaults the configuration registers and spi state machine. cs ? pin 25 chip select input pin, active low. sclk ? pin 26 serial clock input pin. maximum 4.096 mhz. sdi ? pin 27 serial data input pin. data expected valid on rising edge of sclk, transi tion on falling edge. sdo ? pin 28 serial data output pin. data valid on rising edge of sclk, transition on falling edge. 5.2 spi serial transactions following reset, master m ode serial transactions to cs5374 assert cs and write serial clocks to sclk while writing serial data into sdi or reading serial data out from sdo. the cs5374 serial port operates in spi mode 0 (0,0) and reads or writes configuration registers us- ing standard 8-bit spi opcod es. each individual se- rial transaction is 24-bits long and is generated by concatenating an 8-bit spi command opcode, an 8- bit register address, and an 8-bit data byte as shown in figure 16 on page 22. the cs5374 spi state mach ine requires 24 clocks with cs asserted to fully shift out the spi data or else spi clock synchronization can be lost. the cs5376a spi 2 hardware ge nerates 24 clocks per transaction and will keep the cs5374 serial port synchronized at all times. however, if another spi master is used and clock synchronization is lost, two methods are available to recover: 1. hold cs high (inactive) a nd apply 24 clocks to shift out any cached spi da ta bits. this method re- tains the existing cs5374 re gister configuration. ... or ... 2. apply a hardware reset (toggle rst ) and then rewrite all cs5374 register configuration values. sclk sdo sdi pin logic spi figure 15. spi interface block diagram configuration cs registers hardware serial rst
cs5374 cs5374 22 sclk sdi figure 16. cs5374 (slave) serial transactions with cs5376a (master) cs sdo cycle sdi 0x02 addr data sdo sdi sdo cs5374 spi write fr om cs5376a spi2 cs5374 spi read from cs5376a spi2 cs cs 0x03 addr data instruction opcode address definition write 0x02 addr[7:0] write spi register specified by the address in addr. read 0x03 addr[7:0] read spi register specified by the address in addr. msb lsb x 61 2345 msb lsb 61 2345 18 27 6543 spi mode 0 transaction details spi2cmd[15:8] spi2cmd[7:0] spi2dat[23:16] spi2cmd[15:8] spi2cmd[7:0] spi2dat[23:16]
cs5374 cs5374 23 5.3 spi registers the cs5374 spi registers ar e 8-bit registers that control the cs5374 hardwa re configuration. see ?spi tm register summary? on page 34 for de- tailed bit definitions of the spi registers listed in table 2. 5.3.1 version 0x00 the version register indi cates the hardware re- vision of the cs5374 device. read only. ? reset condition : 0100_0001 (0x41) ? normal operation : 0100_0001 (0x41) ? power down operation : 0100_0001 (0x41) 5.3.2 amp1cfg 0x01 the amp1cfg register controls the amplifier mux and gain settings for channel 1. it also en- ables pwdn mode for the channel 1 amplifier plus enables the guard output for channels 1 & 2. ? reset condition : 0000_0000 ? normal operation : 00mm_0ggg ? power down operation : 1000_0000 5.3.3 amp2cfg 0x02 the amp2cfg register controls the amplifier mux and gain settings for channel 2. it also en- ables pwdn mode for the channel 2 amplifier. ? reset condition : 0000_0000 ? normal operation : 00mm_0ggg ? power down operation : 1000_0000 name addr. type # bits description version 0x00 r 8 device version id amp1cfg 0x01 r/w 8 amplifier 1 configuration amp2cfg 0x02 r/w 8 amplifier 2 configuration adccfg 0x03 r/w 8 modulator 1 & 2 configuration pwrcfg 0x04 r/w 8 power configuration table 2. spi configuration registers gain selection gain2 gain1 gain0 1x 0 0 0 2x 0 0 1 4x 0 1 0 8x 0 1 1 16x 1 0 0 32x 1 0 1 64x 1 1 0 reserved 1 1 1 input selection mux1 mux0 800 termination 0 0 ina only 1 0 inb only 0 1 ina + inb 1 1 table 3. digital selections fo r gain and input mux control
cs5374 cs5374 24 5.3.4 adccfg 0x03 the adccfg register can disable modulator ofst and enable hp mode . it also enables pwdn mode for the channel 1 & 2 modulators. ? reset condition : 0000_0000 ? normal operation : 0100_0000 ? power down operation : 0011_0000 5.3.5 pwrcfg 0x04 the pwrcfg register can vary bias currents for the amplifier and modulator to minimize power consumption. ? reset condition : 0000_0000 ? normal operation : 1000_1111 ? power down operation : 0000_0000 5.4 example: cs5374 configuration by an external spi master any spi master that suppor ts mode 0 (0,0) commu- nication can write and read the configuration regis- ters and control cs5374. the following example spi read and write transac- tions show how to conf igure the cs5374 for nor- mal operation. spi write transactions transaction cs5374 spi write description 01 si: 02 | 01 | 20 so: ----------------- write amp1cfg register (0x01). ch1 ina enabled, 1x gain (0x20). 02 si: 02 | 02 | 20 so: ----------------- write amp2cfg register (0x02). ch2 ina enabled, 1x gain (0x20). 03 si: 02 | 03 | 40 so: ----------------- write adccfg register (0x03). normal operation (0x40). 04 si: 02 | 04 | 8f so: ----------------- write pwrcfg register (0x04). normal operation (0x8f). spi read transactions transaction cs5374 spi read description 01 si: 03 | 00 | 00 so: ---------- | 41 read version register (0x00). returned data byte on the so pin. 02 si: 03 | 01 | 00 so: ---------- | 20 read amp1cfg register (0x01). returned data byte on the so pin. 03 si: 03 | 02 | 00 so: ---------- | 20 read amp2cfg register (0x02). returned data byte on the so pin. 04 si: 03 | 03 | 00 so: ---------- | 40 read adccfg register (0x03). returned data byte on the so pin. 05 si: 03 | 04 | 00 so: ---------- | 8f read pwrcfg register (0x04). returned data byte on the so pin. table 4. example spi transactions to write and read the cs5374 configuration registers
cs5374 cs5374 25 5.5 example: cs5374 configuration by the cs5376a spi 2 port the cs5374 spi port was designed to connect to the cs5376a secondary spi 2 port as shown in figure 12 on page 15. the cs5376a spi 2 hardware is controlled by writing internal digital filter registers spi2ctrl, spi2cmd, and spi2dat through a primary spi 1 port. chip selects are enabled by writing the gpcfg0 digital filter register prior to initiating spi 2 transactions. configuring cs5374 using spi 2 is more complex than using an external spi master, but has the ad- vantage of a single standa rdized hardware interface (the primary spi 1 port on cs5376a) to control the entire chipset. 5.5.1 cs5376a spi 1 transactions the cs5376a primary spi 1 port is controlled by an external spi master writing commands and data into the spi 1 registers (spicmd, spidat1, and spidat2). serial transactions into the cs5376a primary spi 1 port start wi th an spi opcode, fol- lowed by an spi address, a nd then data bytes writ- ten starting at that spi address. these data bytes contain internal comma nds to write the cs5376a digital filter registers th at control the spi 2 hard- ware and enable the chip selects. a full description of how to write the cs5376a in- ternal digital filter regi sters using th e primary spi 1 port is described in the cs5376a data sheet. gpio register certain gpio pins on the cs5376a have dual-use as chip selects for the spi 2 port. the gpio0:cs0 and gpio1:cs1 pins are recommended as dedicat- ed chip selects when connecting two cs5374 de- vices to the cs5376a spi 2 port. to operate the cs0 and cs1 pins as spi 2 chip selects they must be programmed as outputs in the gpcfg0 digital filter register, as shown in table 5. spi2 registers three digital filter re gisters control the cs5376a spi 2 hardware. the spi2cm d register is 16-bits wide and contains the fi rst two bytes of the spi 2 transaction, the spi opcode and spi address, in the lower two bytes (i.e. 0x000204). table 5. example cs5376a spi 1 transactions to write and read the gpcfg0 register transaction cs5376a primar y spi 1 write description 01 mosi: 02 | 03 | 00 00 01 | 00 00 0e | 03 ff ff miso: ----------------------------------------------------------- spi command : 0x02 : write spi address : 0x03 : spicmd spicmd : 0x000001 : write register spidat1 : 0x00000e : gpcfg0 spidat2 : 0x03ffff : cs as output 02 delay 1ms, monitor sint , or poll e2dreq see the cs5376a data sheet. 03 mosi: 02 | 03 | 00 00 02 | 00 00 0e | 00 00 00 miso: ----------------------------------------------------------- spi command : 0x02 : write spi address : 0x03 : spicmd spicmd : 0x000002: read register spidat1 : 0x00000e : gpcfg0 spidat2 : 0x000000 : dummy 04 delay 1ms, monitor sint , or poll e2dreq see the cs5376a data sheet. 05 mosi: 03 | 06 |---------------| miso: -------------| 03 ff ff | spi command : 0x03 : read spi address : 0x06 : spidat1 spidat1 : 0x03ffff : gpcfg0
cs5374 cs5374 26 the spi2dat register is 24-bits wide and can con- tain up to three bytes of data to follow the spi op- code and address. for configuring the cs5374, however, only one data byte per register address is required and is written aligned with the upper byte (i.e. 0x8f0000). the spi2ctrl register is 24-bits wide and config- ures/controls the spi 2 ha rdware, with bit assign- ments detailed in the cs5376a data sheet. if the gpio:cs0 and gpio1:cs1 pins are used as chip selects, separate spi2ctrl values can initiate se- rial transactions to each device (i.e. 0x3f0161, 0x3f4162). tables 6, 7, and 8 show the cs5376a primary spi 1 transactions required to write the spi 2 digi- tal filter registers and configure two cs5374 devic- es for normal operation using the cs0 and cs1 chip selects. table 6. example cs5376a spi 1 transactions to write the cs5374 amp1cfg register transaction cs5376a primary spi 1 write description 01 mosi: 02 | 03 | 00 00 01 | 00 00 11 | 00 02 01 miso: ----------------------------------------------------------- spi command : 0x02 : write spi address : 0x03 : spicmd spicmd : 0x000001 : write register spidat1 : 0x000011 : spi2cmd spidat2 : 0x000201 : write amp1cfg 02 delay 1ms, monitor sint , or poll e2dreq see the cs5376a data sheet. 03 mosi: 02 | 03 | 00 00 01 | 00 00 12 | 20 00 00 miso: ----------------------------------------------------------- spi command : 0x02 : write spi address : 0x03 : spicmd spicmd : 0x000001: write register spidat1 : 0x000012 : spi2dat spidat2 : 0x200000 : ina, x1 gain 04 delay 1ms, monitor sint , or poll e2dreq see the cs5376a data sheet. 05 mosi: 02 | 03 | 00 00 01 | 00 00 10 | 3f 01 61 miso: ----------------------------------------------------------- spi command : 0x02 : write spi address : 0x03 : spicmd spicmd : 0x000001: write register spidat1 : 0x000010 : spi2ctrl spidat2 : 0x3f0161 : cs0 transaction 06 delay 1ms, monitor sint , or poll e2dreq see the cs5376a data sheet. 07 mosi: 02 | 03 | 00 00 01 | 00 00 10 | 3f 41 62 miso: ----------------------------------------------------------- spi command : 0x02 : write spi address : 0x03 : spicmd spicmd : 0x000001: write register spidat1 : 0x000010 : spi2ctrl spidat2 : 0x3f4162 : cs1 transaction
cs5374 cs5374 27 transaction cs5376a primary spi 1 write description 01 mosi: 02 | 03 | 00 00 01 | 00 00 11 | 00 02 02 miso: ----------------------------------------------------------- spi command : 0x02 : write spi address : 0x03 : spicmd spicmd : 0x000001 : write register spidat1 : 0x000011 : spi2cmd spidat2 : 0x000202 : write amp2cfg 02 delay 1ms, monitor sint , or poll e2dreq see the cs5376a data sheet. 03 mosi: 02 | 03 | 00 00 01 | 00 00 12 | 20 00 00 miso: ----------------------------------------------------------- spi command : 0x02 : write spi address : 0x03 : spicmd spicmd : 0x000001: write register spidat1 : 0x000012 : spi2dat spidat2 : 0x200000 : ina, x1 gain 04 delay 1ms, monitor sint , or poll e2dreq see the cs5376a data sheet. 05 mosi: 02 | 03 | 00 00 01 | 00 00 10 | 3f 01 61 miso: ----------------------------------------------------------- spi command : 0x02 : write spi address : 0x03 : spicmd spicmd : 0x000001: write register spidat1 : 0x000010 : spi2ctrl spidat2 : 0x3f0161 : cs0 transaction 06 delay 1ms, monitor sint , or poll e2dreq see the cs5376a data sheet. 07 mosi: 02 | 03 | 00 00 01 | 00 00 10 | 3f 41 62 miso: ----------------------------------------------------------- spi command : 0x02 : write spi address : 0x03 : spicmd spicmd : 0x000001: write register spidat1 : 0x000010 : spi2ctrl spidat2 : 0x3f4162 : cs1 transaction table 7. example cs5376a spi 1 tran sactions to write amp2cfg and adccfg transaction cs5376a primary spi 1 write description 01 mosi: 02 | 03 | 00 00 01 | 00 00 11 | 00 02 03 miso: ----------------------------------------------------------- spi command : 0x02 : write spi address : 0x03 : spicmd spicmd : 0x000001 : write register spidat1 : 0x000011 : spi2cmd spidat2 : 0x000203 : write adccfg 02 delay 1ms, monitor sint , or poll e2dreq see the cs5376a data sheet. 03 mosi: 02 | 03 | 00 00 01 | 00 00 12 | 40 00 00 miso: ----------------------------------------------------------- spi command : 0x02 : write spi address : 0x03 : spicmd spicmd : 0x000001: write register spidat1 : 0x000012 : spi2dat spidat2 : 0x400000 : normal operation 04 delay 1ms, monitor sint , or poll e2dreq see the cs5376a data sheet. 05 mosi: 02 | 03 | 00 00 01 | 00 00 10 | 3f 01 61 miso: ----------------------------------------------------------- spi command : 0x02 : write spi address : 0x03 : spicmd spicmd : 0x000001: write register spidat1 : 0x000010 : spi2ctrl spidat2 : 0x3f0161 : cs0 transaction 06 delay 1ms, monitor sint , or poll e2dreq see the cs5376a data sheet. 07 mosi: 02 | 03 | 00 00 01 | 00 00 10 | 3f 41 62 miso: ----------------------------------------------------------- spi command : 0x02 : write spi address : 0x03 : spicmd spicmd : 0x000001: write register spidat1 : 0x000010 : spi2ctrl spidat2 : 0x3f4162 : cs1 transaction
cs5374 cs5374 28 table 8. example cs5376a spi 1 transactio ns to write the cs5374 pwrcfg register transaction cs5376a primary spi 1 write description 01 mosi: 02 | 03 | 00 00 01 | 00 00 11 | 00 02 04 miso: ----------------------------------------------------------- spi command : 0x02 : write spi address : 0x03 : spicmd spicmd : 0x000001 : write register spidat1 : 0x000011 : spi2cmd spidat2 : 0x000204 : write pwrcfg 02 delay 1ms, monitor sint , or poll e2dreq see the cs5376a data sheet. 03 mosi: 02 | 03 | 00 00 01 | 00 00 12 | 8f 00 00 miso: ----------------------------------------------------------- spi command : 0x02 : write spi address : 0x03 : spicmd spicmd : 0x000001: write register spidat1 : 0x000012 : spi2dat spidat2 : 0x8f0000 : normal operation 04 delay 1ms, monitor sint , or poll e2dreq see the cs5376a data sheet. 05 mosi: 02 | 03 | 00 00 01 | 00 00 10 | 3f 01 61 miso: ----------------------------------------------------------- spi command : 0x02 : write spi address : 0x03 : spicmd spicmd : 0x000001: write register spidat1 : 0x000010 : spi2ctrl spidat2 : 0x3f0161 : cs0 transaction 06 delay 1ms, monitor sint , or poll e2dreq see the cs5376a data sheet. 07 mosi: 02 | 03 | 00 00 01 | 00 00 10 | 3f 41 62 miso: ----------------------------------------------------------- spi command : 0x02 : write spi address : 0x03 : spicmd spicmd : 0x000001: write register spidat1 : 0x000010 : spi2ctrl spidat2 : 0x3f4162 : cs1 transaction
cs5374 cs5374 29 6. power modes the cs5374 amplifiers and modulators have three power modes. normal operation, power down with mclk enabled, and power down with mclk dis- abled. power down mode is cont rolled by pwdn bits in the spi registers, and ar e active high. when pwdn is enabled, internal circuitry is disabled, the analog inputs and outputs go high-im pedance, and the de- vice enters a micro-power state. 6.1 normal operation with mclk active and th e amplifiers and modula- tors enabled (pwdn = 0) the cs5374 performs normal data acquisition. a differential analog input signal is converted to an oversampled 1-bit ? bit stream at 512 khz. this ? bit stream is then digi- tally filtered an d decimated by the cs5376a de- vice to a high-precision 24-bit output. 6.2 power down, mclk enabled with mclk active and al l amplifiers and modula- tors disabled (pwdn = 1) the cs5374 is placed into a power-down state. during this power-down state the amplifiers and modulators are disabled and all outputs are high im pedance. in this mode power consumption is re duced, but not reduced as low as with mclk inactive, as sections of the dig- ital state machine are kept awake to support spi communications. any unused amplifier/modulator channels can be turned off individually through the configuration registers. 6.3 power down, mclk disabled if mclk is stopped, an in ternal loss-of-clock de- tection circuit automatically places the cs5374 into a power-down state. this power-down state is independent of the amplif ier and modulator inter- nal configuration registers, and is automatically in- voked after approximately 40 s without receiving an incoming mclk edge. during this power-down stat e, the amplifiers and modulators are disabled and all outputs are high impedance. the entire di gital state machine goes inactive but configuration register values are re- tained, with a reset required to clear them. when used with the cs5376a di gital filter, the cs5374 is in this lowest power-down state immediately after reset since mclk is disabled by default. normal operation mclk = on pwdn registers = disabled power down mode mclk = on pwdn registers = enabled power down mode mclk = off pwdn registers = x figure 17. power mode diagram
cs5374 cs5374 30 7. voltage reference the cs5374 modulators re quire a 2.500 v preci- sion voltage reference to be supplied to the vref pins. 7.1 vref power supply to guarantee proper regul ation headroom for the voltage reference device , the voltage reference gnd pin should be connected to va? instead of system ground, as shown in figure 18 . this con- nection results in a vref? voltage equal to va? and a vref+ voltage very near ground potential [(va?) + 2.500 vref]. power supply inputs to the voltage reference device should be bypassed to system ground with 0.1 f capacitors placed as clos e as possible to the power and ground pins. in addition to 0.1 f local bypass capacitors, at least 100 f of bulk capacitance to system ground should be placed on each power supply near the voltage regulator outputs. bypass capacitors should be x7r, c0g, tantalum, or other high-quality diel ectric type. 7.2 vref rc filter a primary concern in selecting a precision voltage reference device is noise performance in the mea- surement bandwidth. the linear technology lt1019ais8-2.5 voltage reference yields accept- able noise levels if the output is filtered with a low- pass rc filter. a separate rc filter is required for each device connected to the voltage reference output. signal- dependent sampling of th e voltage reference by one system device could caus e unwanted tones to ap- pear in the measurement bandwidth of another sys- tem device if a single vref rc filter is common to both. 7.3 vref pcb routing to minimize the possibili ty of outside noise cou- pling into the cs5374 voltage reference input, the vref traces should be rout ed as a differential pair from the large capacitor of the voltage refer- ence rc filter. careful control of the voltage refer- ence source and return currents by routing vref as a differential pair will significantly improve im- munity from external noise. to further improve nois e rejection of the vref differential route, include 0.1 f bypass capaci- tors to system ground as close as possible to the vref+ and vref? pins of the cs5374. 7.4 vref input impedance the switched-capacitor input architecture of the vref inputs results in an input impedance that depends on the internal capacitor size and the mclk frequency. with a 15 pf internal capacitor and a 2.048 mhz mclk, th e vref input imped- ance is approximately 10 to vref+ + from va+ regulator 2.500 v vref 0.1 f to vref- 0.1 f 100 f 0.1 f 0.1 f 0.1 f 100 f 100 f from va- regulator route vref as a differential pair from the 100uf rc filter capacitor figure 18. voltage reference circuit
cs5374 cs5374 31 1 / [(2.048 mhz) x (15 pf)] = 32 k . while the size of the internal capac itor is fixed, the voltage reference input impedanc e can vary with mclk. the voltage reference extern al rc filter series re- sistor creates a voltage di vider with the vref in- put impedance to reduce th e effective applied input voltage. to minimize gain error resulting from this voltage divider effect, the rc filter series resistor should be the minimum si ze recommended in the voltage reference device data sheet. 7.5 vref accuracy the nominal voltage refere nce input is specified as 2.500 v across the vref pins, and all cs5374 gain accuracy specificati ons are measured using a nominal voltage reference input. any variation from a nominal vref i nput will proportionally vary the analog full-scale gain accuracy. since temperature drift of the voltage reference re- sults in gain drift of the analog full-scale amplitude, care should be taken to mi nimize temperature drift effects through careful se lection of passive compo- nents and the voltage refe rence device itself. gain drift specifications of the cs5374 do not include the temperature drift effects of external passive components or of the voltage reference device it- self.
cs5374 cs5374 32 8. power supplies the cs5374 has two positive analog power supply pins (va+), two negati ve analog power supply pins (va?), a digital pow er supply pin (vd+), and a ground pin (gnd). for proper operation, power must be supplied to all power supply pins, and th e ground pin must be con- nected to system ground. the cs5374 digital pow- er supply (vd+) and th e cs5376a digital power supply (vd) must share a common voltage. 8.1 analog power supplies the analog power pins of the cs5374 are to be sup- plied with a total of 5 v between va+ and va? from a bipolar 2.5 v supply. when using bipolar supplies the analog signa l common mode voltage should be biased to 0 v. the analog power supplies are recommended to be bypassed to system ground using 0.1 f x7r type capacitors. the va? supply is connect ed to the cmos sub- strate and as such must remain the most negative applied voltage to preven t potential latch-up condi- tions. it is recommended to clamp the va? supply to system ground using a reverse biased schottky diode to prevent possible latch-up conditions relat- ed to mismatched supply rail initialization. care should be taken to connect the cs5374 ther- mal pad on the bottom of the package to va?, not system ground (gnd), since it internally connects to va? and is expected to be the most negative ap- plied voltage. 8.2 digital power supply the digital power supply across the vd and gnd pins is specified for a +3.3 v power supply. the digital power supply shoul d be bypassed to system ground using a 0.01 f x7r type capacitor. the digital power supply acro ss the vd+ and gnd pins is specified to be +3.3 v. 8.3 power supply bypassing the va+ and va? power supplies should be by- passed to system ground with 0.1 f capacitors placed as close as possible to the power pins of the device. the vd+ power supply should be bypassed to system ground with 0.1 f capacitors placed as close as possible to the pow er pins of the device. bypass capacitors should be x7r, c0g, tantalum, or other high-quality dielectric type. in addition to the local bypa ss capacitors, at least 100 f bulk capacitance to system ground should be placed on each power supply near the voltage cs5374 va+ vd+ va- gnd 0.01 uf 100 uf 0.1 uf 100 uf 100 uf 0.1 uf to va+ regulator to va- regulator to vd regulator va+ va- 0.1 uf 0.1 uf figure 19. power supply diagram
cs5374 cs5374 33 regulator output, with additional power supply bulk capacitance placed among the analog compo- nent route if space permits. 8.4 pcb layers and routing the cs5374 is a high-perf ormance device, and special care must be ta ken to ensure power and ground routing is correct. po wer can be supplied ei- ther through dedicated power planes or routed trac- es. when routing power traces, it is recommended to use a ?star? routing sche me with the star point ei- ther at the voltage regulat or output or at a local power supply bulk capacitor. it is also recommended to dedicate a full pcb layer to a solid ground plane, wi thout splits or routing. all bypass capacitors shoul d connect between the power supply circuit and the solid ground plane as near as possible to the device power supply pins. the cs5374 analog signals ar e differentially rout- ed and do not normally requi re connection to a sep- arate analog ground. however, if a separate analog ground is required, it shoul d be routed using a ?star? routing scheme on a separate layer from the solid ground plane and connected to the ground plane only at a single point . be sure all active de- vices and passive compone nts connected to the separate analog ground are included in the ?star? route to ensure sensitive analog currents do not re- turn through the ground plane. 8.5 power supply rejection power supply rejection of the cs5374 is frequency dependent. the cs5376a digital filter fully rejects power supply noise for fre quencies above the se- lected digital f ilter corner frequency. power supply noise frequencies between dc and the di gital filter corner frequency are reject ed as specified in the ?power supply characteristics? on page 13 . 8.6 scr latch-up considerations it is recommended to c onnect the va? power sup- ply to system ground (gnd) through a reverse-bi- ased schottky diode. at power up, if the va+ power supply ramps up before the va? supply is established, the va- pin voltage could be pulled above ground potential through the cs5374 de- vice. if the va? supply is pulled 0.7 v or more above gnd, scr latch-up can occur. a reverse-bi- ased schottky diode will clamp the va? voltage a maximum of 0.3 v above ground to ensure scr latch-up does not occur at power up. for similar reasons, care should be taken to connect the cs5374 thermal pad on the bottom of the pack- age to va?, not system ground (gnd), since it in- ternally connects to va? a nd is expected to be the most negative applied voltage. 8.7 dc-dc converters many low-frequency meas urement systems are battery powered and util ize dc-dc converters to efficiently generate pow er supply voltages. to minimize interference effects, operate the dc-dc converter at a frequency wh ich is rejected by the digital filter, or operate it synchronous to the mclk rate. a synchronous dc-dc conve rter whose operating frequency is derived from mclk will theoretically minimize the potential for ?b eat frequencies? to ap- pear in the measurement bandwidth. however this requires the source clock to remain jitter free with- in the dc-dc converter circ uitry. if clock jitter can occur within the dc-dc converter (as in a pll- based architecture), it?s better to use a non-syn- chronous dc-dc converter whose switching fre- quency is rejected by the digital filter. during pcb layout, do not place high-current dc- dc converters near sens itive analog components. carefully routing a sepa rate dc-dc ?star? ground will help isolate noisy switching currents away from the sensitive analog components.
cs5374 cs5374 34 9. spi tm register summary the cs5374 configurati on registers contain the hardware configuration settings. name addr. type # bits description version 0x00 r 8 device version id amp1cfg 0x01 r/w 8 amplifier 1 configuration amp2cfg 0x02 r/w 8 amplifier 2 configuration adccfg 0x03 r/w 8 modulator 1 & 2 configuration pwrcfg 0x04 r/w 8 power configuration
cs5374 cs5374 35 9.1 version: 0x00 ( m s b ) 7654321( l s b ) 0 ver7 ver6 ver5 ver4 ver3 ver2 ver1 ver0 rrrrrrrr 01000001 figure 20. hardware ve rsion id register version bit definitions: 7:0 vers hardware revision id register 0x41: revision a address: 0x00 -- not defined (read as 0) r readable wwritable r/w readable and writable bits in bottom rows are reset condition reset condition : 0100_0001 (0x41) : default value normal operation : 0100_0001 (0x41) : default value power down operation : 0100_0001 (0x41) : default value
cs5374 cs5374 36 9.2 amp1cfg: 0x01 ( m s b ) 7654321( l s b ) 0 pwdn1 hp1 mux1_1 mux1_0 guard gain1_2 gain1_1 gain1_0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 figure 21. amplifier 1 configuration register amp1cfg bit definitions: 7 pwdn1 amplifier 1 power down 1: enable 0: disable 6 hp1 amplifier 1 high precision 1: enable 0: disable 5:4 mux1[1:0] input multiplexer 11: ina1 + inb1 10: ina1 only 01: inb1 only 00: 800 ohm termination 3 guard guard output 1: disable 0: enable 2:0 gain1[2:0] amplifier 1 gain 111: reserved 110: 64x 101: 32x 100: 16x 011: 8x 010: 4x 001: 2x 000: 1x address: 0x01 -- not defined (read as 0) r readable wwritable r/w readable and writable bits in bottom rows are reset condition reset condition : 0000_0000 (0x00) : default value normal operation : 00mm_gggg : mux, guard and gain select power down operation : 1000_0000 (0x80) : pwdn enabled
cs5374 cs5374 37 9.3 amp2cfg: 0x02 ( m s b ) 7654321( l s b ) 0 pwdn2 hp2 mux2_1 mux2_0 --- gain2_2 gain2_1 gain2_0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 figure 22. amplifier 2 configuration register amp2cfg bit definitions: 7 pwdn2 amplifier 2 power down 1: enable 0: disable 6 hp2 amplifier 2 high precision 1: enable 0: disable 5:4 mux2[1:0] input multiplexer 11: ina2 + inb2 10: ina2 only 01: inb2 only 00: 800 ohm termination 3--- reserved 2:0 gain2[2:0] amplifier 2 gain 111: reserved 110: 64x 101: 32x 100: 16x 011: 8x 010: 4x 001: 2x 000: 1x address: 0x02 -- not defined (read as 0) r readable wwritable r/w readable and writable bits in bottom rows are reset condition reset condition : 0000_0000 (0x00) : default value normal operation : 00mm_0g gg : mux and gain select power down operation : 1000_0000 (0x80) : pwdn enabled
cs5374 cs5374 38 9.4 adccfg: 0x03 9.5 pwrcfg: 0x04 ( m s b ) 7654321( l s b ) 0 ofst hp pwdn2 pwdn1 --- --- --- --- r/w r/w r/w r/w r/w r/w r/w r/w 00000000 figure 23. modulator 1 & 2 configuration register adccfg bit definitions: 7ofst modulator offset (add -60mv to channel 1, add -35mv to channel 2) 1: disable 0: enable 6 hp modulator high precision 1: enable 0: disable 5 pwdn2 modulator 2 power down 1: enable 0: disable 4 pwdn1 modulator 1 power down 1: enable 0: disable 3:0 --- reserved address: 0x03 -- not defined (read as 0) r readable wwritable r/w readable and writable bits in bottom rows are reset condition reset condition : 0000_0000 (0x00) : default value normal operation : 0100_0000 (0x40) : hp mode enabled power down operation : 0011_0000 (0x30) : pwdn enabled
cs5374 cs5374 39 ( m s b ) 7654321( l s b ) 0 adc_lpwr --- amp_i1_1 amp_i1_0 rough i1_tail amp_i5_1 amp_i5_0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 figure 24. power configuration register pwrcfg bit definitions: 7 adc_lpwr modulator bias 1: reduced current 0: nominal current 6 --- reserved 5:4 amp_i1 amplifier i1 bias 11: 2/3 10: 1/3 01: 4/3 00: nominal current 3 rough modulator rough phase 1: reduced current 0: nominal current 2 i1_tail amplifier i1 tail current 1: reduced current 0: nominal current 1:0 amp_i5 amplifier i5 bias 11: 7/11 10: 9/13 01: 15/13 00: nominal current address: 0x04 --- not defined (read as 0) r readable wwritable r/w readable and writable bits in bottom rows are reset condition. reset condition : 0000_0000 (0x00) : default value normal operation : 1000_1111 (0x8f) : reduced power power down operation : 0000_0000 (0x00) : default value
cs5374 cs5374 40 10. pin descriptions pin name pin number pin type pin description power supplies va+ va? 6, 39 7, 40 i analog power supply. refer to the specified operating conditions. vd+, gnd 32, 31 i digital power supply. refer to the specified operating conditions. differential amplif ier analog inputs ina1+ ina1? 1 2 i channel 1 differential analog input a. selected via serial communications interface. inb1?, inb1+ 3 4 i channel 1 differential analog input b. selected via serial communications interface. inb2+, inb2? 9 10 i channel 2 differential analog input b. selected via serial communications interface. ina2?, ina2+ 11 12 i channel 2 differential analog input a. selected via serial communications interface. ina2- ina2+ 11 12 top-down (though package) view pin 1 location indicators ina1+ ina1- inb1- inb1+ dnc va+ va- dnc inb2+ inb2- 1 2 3 4 5 6 7 mclk msync mdata1 mflag1 36 35 34 33 vd+ gnd mdata2 32 31 30 guard2 out2+ out2- inr2- inf2- inf2+ inr2+ 19 18 17 16 15 14 13 guard1 out1+ out1- inr1- inf1- inf1+ inr1+ 48 47 46 45 44 43 42 8 9 10 nc vref+ vref- 22 21 20 nc nc 24 23 mflag2 sdo sdi 29 28 27 sclk cs 26 25 nc va- va+ 41 40 39 nc rst 38 37 thermal pad connect to va-
cs5374 cs5374 41 differential amplifier analog outputs out1?, out1+ 46 47 o channel 1 differential analog output. guard1 48 o guard output voltage for analog input channel 1. guard2 13 o guard output voltage for analog input channel 2. out2+, out2? 14 15 o channel 2 differential analog output. modulator analog inputs inr1+, inf1+, inf1?, inr1? 42 43 44 45 i channel 1 analog differential rough and fine inputs. from the channel 1 differential anti-alias filter. inr2?, inf2?, inf2+, inr2+ 16 17 18 19 i channel 2 analog differential rough and fine inputs. from the channel 2 differential anti-alias filter. voltage reference vref+, vref? 21 22 i voltage reference input. refer to the specified operating conditions. serial interface cs 25 i chip select. active low. sclk 26 i serial clock. sdi 27 i serial data in to device. sdo 28 o serial data out of device. modulator interface mclk 36 i modulator clock input. msync 35 i modulator sync input. mflag1 33 o channel 1 modulator flag output. mdata1 34 o channel 1 modulator data output. mflag2 29 o channel 2 modulator flag output. mdata2 30 o channel 2 modulator data output. device reset rst 37 i reset. active low. other nc 20, 23, 24, 38, 41 --- no connect. dnc 5, 8 --- do not connect. thermal pad 49 i connect to va?. do not connect to gnd.
cs5374 cs5374 42 11. package dimensions 48-pin qfn (7mm x 7mm)
cs5374 cs5374 43 12. ordering information 13. environmental, manufacturi ng, & handling information * msl (moisture sensitivit y level) as specified by ipc/jedec j-std-020. model number temperature package CS5374-CNZ, lead (pb) free -10 to +70 c 48-pin qfn model number peak reflow temp msl rating* max floor life CS5374-CNZ, lead (pb) free 260 c 3 7 days
cs5374 cs5374 44 14. revision history revision date changes t1 aug 2008 initial release of target data sheet. a1 dec 2008 initial release of advanced data sheet. a2 jan 2009 update to include more complete characterization data. pp1 apr 2009 specify operation for 2.048 mhz mclk and hp mode. add pwrcfg register. update to include more comp lete characterization data. f1 oct 2009 update to include final characterization data. f2 sep 2010 corrected version regi ster default value to 0100 0001 (0x41) ? cs5374, rev a. contacting cirrus logic support for all product questions and inquiries c ontact a cirrus logic sales representative. to find one nearest you go to www.cirrus.com important notice "preliminary" product information describes products that are in production, but for which full characterization data is not ye t available. cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishi ng this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain application s using semiconductor products may in volve potential risks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus products are not designed, auth orized or warranted for use in products surgically implanted into the body, automotive safety, security devices, life support products or other criti- cal applications. inclusion of cirrus products in such applicat ions is understood to be fully at the customer's risk and cir- rus disclaims and makes no warranty, expr ess, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus prod uct that is used in such a manner. if the customer or custom- er's customer uses or permits the use of cirrus products in critica l applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including at- torneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. spi is a trademark of motorola, inc.

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